A delay locked loop circuit (DLL) or phase locked loop circuit is often employed within an integrated circuit device to generate an on-chip clock signal precisely positioned in a desired alignment with an external reference clock.
FIG. 1a illustrates a conventional delay locked loop circuit 100. An external reference clock REFCLK is compared to an on-chip clock signal INTCLK by phase detector 102. Phase detector 102 measures the error or difference between REFCLK and INTCLK and generates voltages on lines 132 and 134. The voltages on lines 132 and 134 indicate whether REFCLK should be adjusted relative to INTCLK. The voltage on line 132 is coupled to p-channel MOSFET 118 of loop filter 104, and the voltage on line 134 is coupled to p-channel MOSFET 120 of loop filter 104.
Loop filter 104 is an integrator or charge pump that averages and smoothes the phase detector output voltages on lines 132 and 134. Loop filter 104 is also a differential circuit that stores loop state or phase lock information as the difference between control voltages stored on capacitors 128 and 130. Capacitors 128 and 130 are coupled to lines 136 and 138, respectively, and to lines 144 and 146, respectively.
The control voltages on lines 136 and 138 are coupled to voltage controlled delay element 106. The difference between the control voltages on lines 136 and 138 indicates an amount of time that voltage controlled delay element 106 should be adjusted such that on-chip clock signal INTCLK is adjusted to a predetermined alignment with external reference clock REFCLK. Voltage controlled delay element 106 is coupled to clock buffer 108. Clock buffer 108 generates on-chip clock signal INTCLK.
Delay locked loop circuit 100 has two operating modes. The first operating mode is a normal operating mode. During the normal operating mode delay locked loop circuit 100 consumes a certain amount of power.
The second operating mode is a low power mode. The lower power mode shuts off REFCLK and eliminates the power dissipated due to REFCLK and/or INTCLK. Delay locked loop circuit 100 consumes considerably less power when operating in the low power mode than when operating in the normal mode.
When delay locked loop circuit 100 operates in the normal operating mode, control signal LPW* is high and p-channel MOSFET 112 is off. P-channel MOSFET 114 is driven by a bias source of I amperes from current source 122. P-channel MOSFETs 114 and 116 form a current mirror circuit. Therefore, a current proportional to I amperes also flows through p-channel MOSFET 116.
The current flowing through p-channel MOSFET 116 is steered by the differential current steering circuit formed by p-channel MOSFETs 118 and 120. When the voltage on line 134 is low and the voltage on line 132 is high, the current flowing through p-channel MOSFET 116 is steered to capacitor 128 and load circuitry 109 when the charging current is greater than the load current of load circuitry 109. Similarly, when the voltage on line 132 is low and the voltage on line 134 is high, the current flowing through p-channel MOSFET 116 is steered to capacitor 130 and load circuitry 109.
FIG. 1b illustrates one embodiment of load circuitry 109 including common mode circuitry 110 and discharging current sources 124 and 126.
FIG. 1c illustrates another embodiment of load circuitry 109 including n-channel MOSFET transistors 140, 142, 144, and 146.
FIG. 2 further illustrates the operation of delay locked loop circuit 100. Waveform A corresponds to the signal on line 132. Waveform B corresponds to the signal on line 134. Waveform C corresponds to the control signal LPW*. Waveform D corresponds to the signal on line 136. Waveform E corresponds to the signal on line 138. Waveforms A-E are illustrative waveforms to aide in the understanding of the operation of delay locked loop circuit 100. They are not actual measured or simulated waveforms.
From time t0 to time t1 delay locked loop circuit 100 is in a locked state and stores loop state information on capacitors 128 and 130. In the locked state, load circuitry 109 sets the common mode voltage on lines 136 and 138, respectively. For one embodiment, waveform D may be approximately 1300 millivolts (mV), and waveform E may be approximately 900 mV. Thus, delayed locked loop circuit 100 may have a starting differential voltage of 400 mV and a starting common mode voltage of 1100 mV.
While delay locked loop circuit 100 is in the locked state, the voltages on lines 132 and 134 may toggle once per clock cycle of REFCLK. Each toggle may cause a change in the voltages stored on capacitors 128 and 130 and lines 136 and 138, as illustrated in FIG. 2.
At time t1, delay locked loop circuit 100 switches to the low power mode. In the low power mode, control signal LPW* is low and p-channel MOSFET 112 is on. P-channel MOSFET 112 pulls the gate of p-channel MOSFET 116 to VDD which cuts off p-channel MOSFET 116. When p-channel MOSFET 116 is off, no charging current is available to be steered by p-channel MOSFETs 118 and 120 to capacitors 128 and 130.
As illustrated in FIG. 2, when no charging current is available from p-channel MOSFET 116 at time t1, load circuitry 109 discharges the voltages stored on capacitors 128 and 130 to ground. Thus, delay locked loop circuit 100 becomes unlocked as the differential loop state information stored on capacitors 128 and 130 collapses or is lost.
When delay locked loop circuit 100 is switched from low power mode to normal operating mode at time t2, the common mode voltage (e.g. 1100 mV) and the differential loop state information on capacitors 128 and 130 must be reacquired. A long period of time is required to reacquire phase lock at time t3. For example, if capacitors 128 and 130 are each approximately 20 picofarads (pF), and the charging current is approximately 10 microamperes (xcexcA), then the time required to reacquire phase lock after switching from low power mode to normal mode may be approximately 2.2 microseconds (xcexcS) (i.e., 1100 mV/(10 xcexcA/20 pF)).
Thus, when low pass filter 104 enters low power mode at time t1 and exits lower power mode at time t2, there is a common mode disturbance or error on lines 136 and 138. As illustrated in FIG. 2, this common mode disturbance is the full common mode voltage. For example, the common mode disturbance is 1100 mV.
One object of the present invention is to provide a delay locked loop circuit having a low pass filter that can quickly switch from low power mode to normal operating mode.
Another object of the present invention is to provide a delay locked loop circuit having a low pass filter that can switch from normal operating mode to low power mode without losing phase lock.
Another object of the present invention is to provide a delay locked loop circuit having a low pass filter that can switch from low power mode to normal operating mode and quickly reacquire phase lock.
Another object of the present invention is to provide a delay locked loop circuit having a low pass filter that can switch from low power mode to normal operating mode without having to reacquire phase lock.
A low pass filter having a first mode of operation and a second mode of operation is described. The low pass filter includes a charging circuit, a capacitor circuit, and low power circuitry coupled to the capacitor circuit and the charging circuit. The capacitor circuit stores a first differential voltage when the low pass filter is operating in the first mode of operation. The capacitor circuit stores a second differential voltage when the low pass filter is operating in the second mode of operation. The second differential voltage is substantially equal to the first differential voltage. The charging circuit may include a charging current source coupled to a current steering circuit. The low pass filter may further include a load circuit coupled to the current steering circuit and the low power circuitry. The low pass filter may be used in a delay locked loop circuit, a phase locked loop circuit, or a duty cycle corrector.
Other features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows.